1. Field of the Invention
The present invention relates to a method for wafer alignment, and more particularly, to a method for increasing alignment accuracy.
2. Description of the Prior Art
Lithographic technologies are key technologies that affect the critical dimensions in semiconductor processes. Most electric circuit patterns are formed by transferring the patterns of photo masks to photoresists in lithographic processes, and thereafter transferring the patterns of photoresists to the material layers of a wafer in etching processes. Thus, several marks are disposed on a wafer to increase alignment accuracy.
Sample wafers with alignment marks are put into product lines for testing alignment accuracy before wafers practically go into mass production. In the lithography process, the photo mask and the wafer are first aligned by an exposure tool using a set of pre-layer alignment marks typically located near an edge or on a scribe line of the wafer surface. Then, the exposure tool illuminates the alignment marks, and the reflected light signal produced by the alignment marks is read by the exposure tool to obtain precise alignment.
“Pre-layer” described in the instant application refers to a material layer processed in a previous lithography step, and “current-layer” described in the instant application refers to a material layer which is to be processed in the current lithography process. The alignment mark usually includes a set of trenches etched in a material layer on a wafer.
After exposure, wafers are developed. It is important to check if the electric circuit pattern in one material layer cooperates with the underlying electric circuit pattern; otherwise, the formed electric circuit may fail. Therefore, accuracy of the alignment is checked in an overlay tool by taking overlay marks on wafers as an overlay reference. Then, offset distances between the pre-layer overlay mark and the current-layer overlay mark can be measured by the overlay tool, and the exposure parameters and development parameters can be adjusted. Generally, the overlay mark is a set of trenches etched in a current material layer, or a set of protrusions on the previous material layer.
Since the above-mentioned alignment mark and overlay mark are respectively measured by different tools, i.e. the exposure tool and the overlay tool, the wafer stages and the detectors in each tool all have their own deviations. In other words, the measured results obtained from a single tool become more complicated due to the addition of the respective deviations and the total deviations become adversely enhanced.